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march 2006 1/139 rev. 4.0 st7262 low speed usb 8-bit mcu with 3 endpoints, flash or rom memory, lvd, wdg, 10-bit adc, 2 timers, sci, spi memories ? 8k or 16k program memory (rom or dual voltage flash) with read-write protection ? in-application and in-circuit programming for flash versions ? 384 to 768 bytes ram (128-byte stack) clock, reset and supply management ? enhanced reset system (power on reset) ? low voltage detector (lvd) ? clock-out capability ? 6 or 12 mhz oscillator (8, 4, 2, 1 mhz internal frequencies) ? 3 power saving modes usb (universal serial bus) interface ? dma for low speed a pplications compliant with usb specification (version 2.0): ? integrated 3.3v voltage regulator and trans- ceivers ? suspend and resume operations ? 3 endpoints up to 31 i/o ports ? up to 31 multifunctional bidirectional i/o lines ? up to 12 external interrupts (3 vectors) ? 13 alternate function lines ? 8 high sink outputs (8 ma@0.4 v/20 ma@1.3 v) ? 2 true open drain pins (n buffer 8 ma@0.4 v) 3 timers ? configurable watchdog timer (8 to 500 ms timeout) ? 8-bit auto reload ti mer (art) with 2 input captures, 2 pwm outputs and external clock ? 8-bit time base unit (tbu) for generating pe- riodic interrupts cascadable with art analog peripheral ? 10-bit a/d converter with up to 8 input pins. 2 communications interfaces ? asynchronous serial communication inter- face ? synchronous serial peripheral interface instruction set ? 8-bit data manipulation ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction ? true bit manipulation nested interrupts development tools ? full hardware/software development package device summary pdip32 shrink so34 shrink lqfp44 pdip42 shrink so20 pdip20 features st72623f2 st72621k4 st72622l2 st72621l4 st72621j4 program memory - bytes 8k 16k 8k 16k 16k ram (stack) - bytes 384 (128) 768 (128) 384 (128) 768 (128) 768 (128) peripherals usb, watchdog, low voltage detector, 8-bit auto-reload timer, timebase unit, a/d converter serial i/o - spi + sci spi spi + sci i/os 11212331 operating supply 4.0v to 5.5v (low voltage 3.0v to 5.5v rom versions available) operating temperature 0c to +70c packages pdip20/so20 pdip32 so34 pdip42/lqfp44 1
table of contents 139 2/139 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pcb layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 clocks and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3 timebase unit (tbu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 10.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.6 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
table of contents 139 3/139 10.7 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.10timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.11communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 117 12.1210-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 128 14.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2 device ordering inform ation and transfer of customer code . . . . . 128 14.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.1 a/ d converter accuracy for first conversion . . . . . . . . . . . . . . . . . . . . 135 15.2 a/d converter conversion speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.3 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.4 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.5 halt mode power consumption with adc on . . . . . . . . . . . . . . . . . . . . . . . . . 136 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
st7262 4/139 1 introduction the st7262 and st72f62 devices are members of the st7 microcontroller family designed for usb applications. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st7262 devices are rom versions. the st72f62 versions feature dual-voltage flash memory with flash programming capa- bility. under software control, all devices can be placed in wait, slow, or halt mode, reducing power consumption when the app lication is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer bo th power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. general block diagram 8-bit core alu address and data bus oscin oscout reset port b usb sie port a sci port c spi pb7:0 (8 bits) pc7:0 (8 bits) oscillator internal clock control ram (384, pa7:0 (8 bits) v ss v dd power supply program (8 or 16k bytes) lvd 10-bit adc memory watchdog usbdp usbdm usbvcc pwm art usb dma v ssa v dda port d pd6:0 (7 bits) time base unit v pp or 768 bytes) 1
st7262 5/139 2 pin description figure 2. 44-pin lqfp and 42-pin sdip package pinouts 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 pd6 pd5 oscout oscin it9 / pc2 it10 / sck / pc3 it11 / ss / pc4 it12 / miso / pc5 mosi / pc6 pd1 v pp pd2 pd3 pd4 pc7 pd0 v dda usbvcc pb1 (hs) / rdi pb0 (hs) / mco pa7 / ain7 pa6 / ain6 pa5 / ain5 pa4 / ain4 pa3 / ain3 / it4 pa0 / ain0 / it1 / usboe reset v ssa usbdm usbdp pa1 / ain1 / it2 pa2 / ain2 / it3 21 20 17 18 19 it8 / pwm1 / pb7 (hs) pc0 pc1 v dd v ss 26 25 24 23 22 pb6 (hs) / pwm0 / it7 / iccdata pb5 (hs) / artic2 / it6 / iccclk pb4 (hs) / artic1 / it5 pb3 (hs) / artclk pb2 (hs) / tdo oscout oscin it9 / pc2 it10 / sck / pc3 it11 / ss / pc4 it12 / miso / pc5 mosi / pc6 pd1 v pp pc7 pd0 it8 / pwm1 / pb7 pc0 pc1 v dd v ss artclk / pb3 (hs) it5 / artic1 / pb4 (hs) iccclk / it6 / artic2 / pb5 (hs) iccdata /it7 / pwm0 / pb6 (hs) n.c. tdo / pb2 (hs) pb1 (hs) / rdi pb0 (hs) / mco pa7 / ain7 pa6 / ain6 pa5 / ain5 pa4 / ain4 pa3 / ain3 / it4 pa0 / ain0 / it1 / usboe reset pa1 / ain1 / it2 pa2 / ain2 / it3 v dda usbvcc v ssa usbdm usbdp pd3 pd4 reserved* pd6 pd5 pd2 * pin 39 of the lqfp44 package must be left unconnected.
st7262 6/139 pin description (cont?d) figure 3. 34-pin so and 32-pin sdip package pinouts 28 27 26 25 24 23 22 21 20 19 18 29 30 31 32 pc4 / ss / int11 pc5 / miso / it12 pa4 / ain4 pa3 / ain3 / it4 pa2 / ain2 / it3 pa1 / ain1 / it2 pa0 / ain0 / it1 / usboe v ssa usbdm usbvcc v dda v pp reset pc6 / mosi usbdp pc7 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 it10 / sck / pc3 it9 / pc2 ain7 / pa7 mco / pb0 (hs) rdi / pb1 (hs) tdo / pb2 (hs) artclk / pb3 (hs) it5 / artic1 / pb4 (hs) iccclk / it6 /artic2 / pb5 (hs) it8 / pwm1 / pb7 (hs) v dd v ss oscout oscin iccdata / it7 / pwm0 / pb6 (hs) pa5 / ain5 ain6 / pa6 33 34 17 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 it10 / sck / pc3 it9 / pc2 ain7 / pa7 mco / pb0 (hs) rdi / pb1 (hs) tdo / pb2 (hs) artclk / pb3 (hs) it5 / artic1 / pb4 (hs) iccclk / it6 / artic2 / pb5 (hs) it8 / pwm1 / pb7 (hs) v dd v ss oscout oscin iccdata / it7 / pwm0 / pb6 (hs) ain6 / pa6 pc4 / ss / int11 pc5 / miso / it12 pa4 / ain4 pa3 / ain3 / it4 pa2 / ain2 / it3 pa1 / ain1 / it2 pa0 / ain0 / it1 / usboe v ssa usbdm usbvcc v dda v pp reset pc6 / mosi usbdp pa5 / ain5 pc1
st7262 7/139 figure 4. 20-pin so20 package pinout figure 5. 20-pin dip20 package pinout 14 13 12 11 15 16 17 18 oscin oscout pb7 (hs) / pwm1 / it8 pb6 (hs) / pwm0 / it7/ iccdata usbvcc v dd v pp usbdp 1 2 3 4 5 6 7 8 9 10 it3 / ain2 / pa2 pb0 (hs) / mco pb1 (hs) pb2 (hs) pb3 (hs) / artclk pb4 (hs) / artic1 / it5 reset it2 / ain1 / pa1 19 20 usboe/ it1 / ain0/ pa0 v ss usbdm pb5 (hs) / artic2 / it6 / iccclk 14 13 12 11 15 16 17 18 oscin oscout pb7 (hs) / pwm1 / it8 pb6 (hs) / pwm0 / it7/iccdata usbvcc v dd v pp usbdp 1 2 3 4 5 6 7 8 9 10 it5 / artic1 / pb4 (hs) mco / pb0 (hs) pb1 (hs) pb2 (hs) reset it2 / ain1/ pa1 19 20 usboe / it1 / ain0 / pa0 v ss usbdm pb5 (hs) / artic2 / it6 / iccclk it3 / ain2 / pa2 artclk / pb3 (hs)
st7262 8/139 pin description (cont?d) legend / abbreviations: type: i = input, o = output, s = supply input level: a = dedicated analog input input level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only) port configuration capabilities: ? input:float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge ) , ana = analog ? output: od = open drain, t = true open drain (n buffer 8ma@0.4 v), pp = push-pull table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function lqfp44 dip42 so34 dip32 so20 dip20 input output input output float wpu int ana od pp 1 6 29 28 9 14 v pp sx flash programming voltage (12v), must be tied low in user mode. 27----pd1 i/oc t xx port d1 38----pd0 i/oc t xx port d0 4931- - -pc7 i/oc t xx port c7 5 10 32 30 - - pc6/mosi i/o c t xx port c6 spi master out / slave in 1) 6 11 33 31 - - pc5/miso/it12 i/o c t xx x port c5 spi master in / slave out 1) / interrupt 12 input 7123432 - -pc4/ss /it11 i/o c t xx x port c4 spi slave select (active low) 1) / interrupt 11 input 8 13 1 1 - - pc3/sck/it10 i/o c t xx x port c3 spi serial clock 1) / interrupt 10 input 9142 2 - -pc2/it9 i/oc t xx x port c2 interrupt 9 input 10 15 3 3 11 16 oscin these pins are used connect an external clock source to the on- chip main oscillator. 11 16 4 4 12 17 oscout 12 17 5 5 4 9 v ss s digital ground voltage 13 18 6 6 8 13 v dd s digital main power supply volt- age 14 19 7 - - - pc1 i/o c t xt port c1 15 20 - - - - pc0 i/o c t xt port c0 16 21 8 7 13 18 pb7/pwm1/it8/ rx_sez/da- taout/da9 i/o c t hs x \ x port b7 art pwm output 1/ interrupt 8 input 17 - - n.c. not connected
st7262 9/139 18 22 9 8 14 19 pb6/pwm0/it7/ iccdata i/o c t hs x \ x port b6 art pwm output 0/ interrupt 7 input/in- circuit communica- tion data 19 23 10 9 15 20 pb5/artic2/it6/ iccclk i/o c t hs x / x port b5 art input capture 2/ interrupt 6 input/ in-circuit communi- cation clock 20 24 11 10 16 1 pb4/artic1/it5 i/o c t hs x / x port b4 art input capture 1/interrupt 5 input 21 25 12 11 17 2 pb3/artclk i/o c t hs x x port b3 art clock input 22 26 13 12 18 3 pb2/tdo i/o c t hs x x port b2 sci transmit data output 1) 23 27 14 13 19 4 pb1/rdi i/o c t hs x x port b1 sci receive data input 1) 24 28 15 14 20 5 pb0/mco i/o c t hs x x port b0 cpu clock output 25 29 16 15 - - pa7/ain7 i/o c t xxx port a7 adc analog input 7 26 30 17 16 - - pa6/ain6 i/o c t xxx port a6 adc analog input 6 27 31 18 17 - - pa5/ain5 i/o c t xxx port a5 adc analog input 5 28 32 19 18 - - pa4/ain4 i/o c t xxx port a4 adc analog input 4 29 33 20 19 - - pa3/ain3/it4 i/o c t x\xx port a3 adc analog input 3/ interrupt 4 input 30 34 21 20 1 6 pa2/ain2/it3 i/o c t x\xx port a2 adc analog input 2/ interrupt 3 input 31 35 22 21 2 7 pa1/ain1/it2 i/o c t x\xx port a1 adc analog input 1/ interrupt 2 input 32 36 23 22 3 8 pa0/ain0/it1/ usboe i/o c t x\xx port a0 adc analog input 0/ interrupt 1 input/ usb output enable 33 37 30 29 10 15 reset i/o c top priority non maskable inter- rupt (active low) 34 38 24 23 - - v ssa s analog ground voltage, must be connected externally to v ss . 35 39 25 24 5 10 usbdm i/o usb bidirectional data (data -) 36 40 26 25 6 11 usbdp i/o usb bidirectional data (data +) 37 41 27 26 7 12 usbvcc s usb power supply 3.3v output 38 42 28 27 - - v dda s analog power supply voltage, must be connected externally to v dd . 39 - - - - - reserved must be left unconnected. 40 1 - - - - pd6 i/o c t xx port d6 41 2 - - - - pd5 i/o c t xx port d5 42 3 - - - - pd4 i/o c t xx port d4 pin n pin name type level port / control main function (after reset) alternate function lqfp44 dip42 so34 dip32 so20 dip20 input output input output float wpu int ana od pp
st7262 10/139 note 1: peripheral not present on all devices. refer to ?device summary? on page 1 . 2.1 pcb layout recommendation in the case of dip20 devices the user should lay- out the pcb so that the dip20 st7262 device and the usb connector are centered on the same axis ensuring that the d- and d+ lines are of equal length. refer to figure 6 figure 6. recommended pcb layout for usb interface with dip20 package 43 4 - - - - pd3 i/o c t xx port d3 44 5 - - - - pd2 i/o c t xx port d2 pin n pin name type level port / control main function (after reset) alternate function lqfp44 dip42 so34 dip32 so20 dip20 input output input output float wpu int ana od pp 14 13 12 11 15 16 17 18 usbvcc usbdp 1 2 3 4 5 6 7 8 9 10 19 20 usbdm usb connector ground ground st7262 1.5kohm pull-up resistor
st7262 11/139 3 register & memory map as shown in the figure 7 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 64 bytes of register locations, 768 bytes of ram and up to 16 kbytes of user program memory. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as ?re- served? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. figure 7. memory map 0000h program memory interrupt & reset vectors hw registers bfffh 0040h 003fh (see table 2 ) c000h ffdfh ffe0h ffffh (see table 6 ) 0340h reserved 033fh short addressing ram (zero page) or stack 017fh 0040h 00ffh 768 bytes ram e000h 8 kbytes (128 bytes) 16 kbytes 384 bytes ram 64 bytes 01bfh 16-bit addressing ram short addressing ram (zero page) 017fh 0040h 00ffh 448 bytes 033fh 16-bit addressing ram 16-bit addressing ram or stack (128 bytes) 16-bit addressing ram 192 bytes 192 bytes
st7262 12/139 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h port a padr paddr port a data register port a data direction register 00h 1) 00h r/w 2) r/w 2) 0002h 0003h port b pbdr pbddr port b data register port b data direction register 00h 1) 00h r/w 2) r/w 2) 0004h 0005h port c pcdr pcddr port c data register port c data direction register 00h 1) 00h r/w 2) r/w 2) 0006h 0007h port d pddr pdddr port d data register port d data direction register 00h 1) 00h r/w 2) r/w 2) 0008h itrfre1 interrupt register 1 00h r/w 0009h misc miscellaneous register 00h r/w 000ah 000bh 000ch adc adcdrmsb adcdrlsb adccsr adc data register (bit 9:2) adc data register (bit 1:0) adc control status register 00h 00h 00h read only read only r/w 000dh wdg wdgcr watchdog control register 7fh r/w 000eh 0010h reserved area (3 bytes) 0011h 0012h 0013h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w read only 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch pwm art pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register art input capture control/status register art input capture register 1 art input capture register 2 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w read only read only 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h sci scierpr scietpr scisr scidr scibrr scicr1 scicr2 sci extended receive prescaler register sci extended transmit prescaler register reserved area sci status register sci data register sci baud rate register sci control register 1 sci control register 2 00h 00h -- c0h xxh 00h x000 0000b 00h r/w r/w read only r/w r/w r/w r/w
st7262 13/139 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always be kept at their reset value. 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h usb usbpidr usbdmar usbidr usbistr usbimr usbctlr usbdaddr usbep0ra usbep0rb usbep1ra usbep1rb usbep2ra usbep2rb usb pid register usb dma address register usb interrupt/dma register usb interrupt status register usb interrupt mask register usb control register usb device address register usb endpoint 0 register a usb endpoint 0 register b usb endpoint 1 register a usb endpoint 1 register b usb endpoint 2 register a usb endpoint 2 register b x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0032h to 0035h reserved area (4 bytes) 0036h 0037h tbu tbucv tbucsr tbu counter value register tbu control/status register 00h 00h r/w r/w 0038h flash fcsr flash control/status register 00h r/w 0039h itrfre2 interrupt register 2 00h r/w 003ah to 003fh reserved area (6 bytes) address block register label register name reset status remarks
st7262 14/139 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features three flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. ? iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection register access securi ty system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 3 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 8 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 3. sectors available in flash devices 4.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. even if no protection can be considered as to- tally unbreakable, the feature provides a very high level of protection for a general purpose microcon- troller. in flash devices, this protection is removed by re- programming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. figure 8. memory map and sector address flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k
st7262 15/139 flash program memory (cont?d) 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 9 ). these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input/output serial data pin ? iccsel/v pp : programming voltage ? osc1(or oscin): main clock input for exter- nal source (optional) ?v dd : application board power supply (see fig- ure 9 , note 3) figure 9. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icc session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or os- cin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator ca pability need to have osc2 grounded in this case. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k ? v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4)
st7262 16/139 flash program memory (cont?d) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circu it communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 9 ). for more details on the pin locations, refer to the device pinout de- scription. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci or other type of serial interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.8 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. 70 00000000
st7262 17/139 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 10. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st7262 18/139 central processing unit (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1
st7262 19/139 cpu registers (cont?d) stack pointer (sp) read/write reset value: 017fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11 ). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 11. stack manipulation example 15 8 00000001 70 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h
st7262 20/139 6 clocks and reset 6.1 clock system 6.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu ) is de- rived from the external oscillator frequency (f osc ), by dividing by 3 and multiplying by 2. by setting the osc12/6 bit in the option byte, a 12 mhz external clock can be used giving an internal frequency of 8 mhz while maintaining a 6 mhz clock for usb (re- fer to figure 14 ). the internal clock signal (f cpu ) consists of a square wave with a duty cycle of 50%. it is further divided by 1, 2, 4 or 8 depending on the slow mode selection bits in the miscellaneous register (sms[1:0]) the internal osc illator is designed to operate with an at-cut parallel resonant quartz or ceramic res- onator in the frequency range specified for f osc . the circuit shown in figure 13 is recommended when using a crystal, and table 4 lists the recom- mended capacitors. the crystal and associated components should be mounted as close as pos- sible to the input pins in order to minimize output distortion and start- up stabilization time. table 4. recommended values for 12 mhz crystal resonator note: r smax is the equivalent seri al resistor of the crystal (see crystal specification). note: when a crystal is used, and to not over- stress the crystal, st recommends to add a serial resistor on the oscout pin to limit the drive level in accordance with th e crystal manufacturer?s specification. please also refer to section 12.5.4 . 6.1.2 external clock input an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 12 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see elec- trical characteristics). 6.1.3 clock output pin (mco) the internal clock (f cpu ) can be output on port b0 by setting the mco bit in the miscellaneous regis- ter. figure 12. external clock source connections figure 13. crystal/ceramic resonator r smax 20 ? 25 ? 70 ? c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m ? 1-10 m ? 1-10 m ? oscin oscout external clock nc oscin oscout c oscin c oscout
st7262 21/139 figure 14. clock block diagram 6.2 reset the reset procedure is used to provide an orderly software start-up or to exit low power modes. three reset modes are provided: a low voltage re- set, a watchdog reset and an external reset at the reset pin. a reset causes the reset vector to be fetched from addresses fffeh and ffffh in order to be loaded into the pc and with program execution starting from this point. an internal circuitry provides a 514 cpu clock cy- cle delay from the time that the oscillator becomes active. 6.2.1 low voltage reset low voltage reset circuitry generates a reset when v dd is: below v it+ when v dd is rising, below v it- when v dd is falling. during low voltage reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes: the low voltage detector can be disabled by set- ting the lvd bit of the option byte. it is recommended to make sure that the v dd supply voltage rises monotonously when the device is ex- iting from reset, to ensure the application functions properly. 6.2.2 watchdog reset when a watchdog rese t occurs, the reset pin is pulled low permitting the mcu to reset other devic- es as when low voltage reset ( figure 15 ). 6.2.3 external reset the external reset is an active low input signal ap- plied to the reset pin of the mcu. as shown in figure 18 , the reset signal must stay low for a minimum of one and a half cpu clock cycles. an internal schmitt trigger at the reset pin is pro- vided to improve noise immunity. figure 15. low voltage reset functional diagram to cpu and f cpu 8/4/2/1 mhz 6 mhz (usb) 12 or peripherals %2 0 1 osc12/6 6 mhz crystal x2 slow mode % sms[1:0] 1/2/4/8 %3 (or 4/2/1/0.5 mhz) mco pin low voltage v dd from watchdog reset reset internal reset reset
st7262 22/139 figure 16. low voltage reset signal output note : typical hysteresis (v it+ -v it- ) of 250 mv is expected. figure 17. temporization timing di agram after an internal reset figure 18. reset timing diagram note: refer to electrical characteristics for values of t ddr , t oxov , v it+ and v it-. reset v dd v it+ v it- v dd addresses $fffe temporization v it+ (514 cpu clock cycles) v dd oscin f cpu ffff fffe pc reset t ddr t oxov 514 cpu clock cycles delay
st7262 23/139 figure 19. reset block diagram note: the output of the external reset circuit must ha ve an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). reset r on v dd watchdog reset lvd reset internal reset pulse generator 200ns filter t w(rstl)out + 128 f osc delay
st7262 24/139 7 interrupts 7.1 introduction the cpu enhanced interrupt management pro- vides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrup t priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 3 non maskable events: reset, trap, tli this interrupt management is based on: ? bit 5 and bit 3 of the cpu cc register (i1:0), ? interrupt software priority registers (isprx), ? fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with th e standard (not nest- ed) cpu interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt so ftware priority level of each interrupt vector (see table 5 ). the process- ing flow is shown in figure 20 . when an interrupt request has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ?interrupt mapping? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume. table 5. interrupt software priority levels figure 20. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt
st7262 25/139 interrupts (cont?d) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: ? the highest software priority interrupt is serviced, ? if several interr upts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 21 describes this decision process. figure 21. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and tli can be considered as having the highest software priority in the deci- sion process. different interrupt vector sources two interrupt source types are managed by the cpu interrupt controller: the non-maskable type (reset, tli, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 20 ). after stacking the pc, x, a and cc registers (except for r eset), the co rresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. tli (top level hardware interrupt) this hardware in terrupt occurs when a specific edge is detected on the dedicated tli pin. caution : a trap instruction must not be used in a tli service routine. trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 20 as a tli. caution: trap can be interrupted by a tli. reset the reset source has the highest priority in the cpu. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitiv ity is software selectable through the itrfre2 register. external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically nanded. peripheral interrupts usually the peripheral interrupts cause the device to exit from halt mode except those mentioned in the ?interrupt mapping? table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will theref ore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
st7262 26/139 interrupts (cont?d) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in ?interrupt mapping? table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with ex it from halt mode capability and it is selected through the same decision proc- ess shown in figure 21 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 22 and figure 23 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 23 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 22. concurrent interrupt management figure 23. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes
st7262 27/139 interrupts (cont?d) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see ?interrupt dedicated instruction set? table). *note : tli, trap and reset events can interrupt a level 3 program. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. ? each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. ? each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. ? level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and tli vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits
st7262 28/139 interrupts (cont?d) interrupt register 1 (itrfre1) address: 0008h - read/write reset value: 0000 0000 (00h) bit 7:0 = itie interrupt enable 0: i/o pin free for general purpose i/o 1: iti external interrupt enabled. note: the corresponding interrupt is generated when: ? a rising edge occurs on the it5/it6 pins ? a falling edge occurs on th e it1, 2, 3, 4, 7 and 8 pins interrupt register 2 (itrfre2) address: 0039h - read/write reset value: 0000 0000 (00h) bit 7:6 = ctl[3:2] it[12:11] interrupt sensitivity these bits are set and cleared by software. they are used to configure the edge and level sensitivity of the it12 and it11 external interrupt pins (this means that both must have the same sensitivity). bit 5:4 = ctl[1:0] it[10:9]1nterrupt sensitivity these bits are set and cleared by software. they are used to configure the edge and level sensitivity of the it10 and it9 external interrupt pins (this means that both must have the same sensitivity). bit 3:0 = itie interrupt enable 0: i/o pin free for general purpose i/o 1: iti external interrupt enabled. 70 it8e it7e it6e it5e it4e it3e it2e it1e 70 ctl3 ctl2 ctl1 ctl0 it12e it11e it10e it9e ctl3 ctl2 it[12:11] sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge ctl1 ctl0 it[10:9] sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
st7262 29/139 interrupts (cont?d) table 6. interrupt mapping table 7. nested interrupts register map and reset values n source block description register label priority order exit from halt address vector reset highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 icp flash start programming nmi interrupt yes fffah-fffbh 1 usb usb end suspend interrupt usbistr yes fff8h-fff9h 2 i/o ports port a external interrupts it[4:1] itrfre1 yes fff6h-fff7h 3 port b external interrupts it[8:5] itrfre1 yes fff4h-fff5h 4 port c external interrupts it[12:9] itrfre2 yes fff2h-fff3h 5 tbu timebase unit interrupt tbucsr no fff0h-fff1h 6 art art/pwm timer interrupt iccsr yes ffeeh-ffefh 7 spi spi interrupt vector spisr yes ffech-ffedh 8 sci sci interrupt vector scisr no ffeah-ffebh 9 usb usb interrupt vector usbistr no ffe8h-ffe9h 10 adc a/d end of conversion interrupt adccsr no ffe6h-ffe7h reserved area ffe0h-ffe5h address (hex.) register label 76543210 0032h ispr0 reset value ext. interrupt port b ext. interrupt port a usb end susp not used i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0033h ispr1 reset value spi art tbu ext. interrupt port c i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0034h ispr2 reset value not used adc usb sci i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0035h ispr3 reset value1111 not used not used i1_13 1 i0_13 1 i1_12 1 i0_12 1
st7262 30/139 8 power saving modes 8.1 introduction there are three power saving modes. slow mode is selected by setting th e sms bits in the miscella- neous register. wait and halt modes may be en- tered using the wfi and halt instructions. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 and multi- plied by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. 8.1.1 slow mode in slow mode, the oscilla tor frequency can be di- vided by a value defined in the miscellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. 8.2 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0, to enable all interrupts. a ll other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 24 . figure 24. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 514 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
st7262 31/139 power saving modes (cont?d) 8.3 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by ex- ecuting the halt instructi on. the internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the condi- tion code register is cleared. thus, any of the ex- ternal interrupts (iti or usb end suspend mode), are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a reset. the oscillator is th en turned on and a stabi- lization time is provided before releasing cpu op- eration. the stabilization time is 514 cpu clock cy- cles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 25. halt mode flow chart n n external interrupt* reset halt instruction 514 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y note: before servicing an in terrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
st7262 32/139 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: ? analog signal input (adc) ? alternate signal input/output for the on-chip pe- ripherals. ? external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input or digital output. 9.2 functional description each port is associated with 2 main registers: ? data register (dr) ? data direction register (ddr) each i/o pin may be programmed using the corre- sponding register bits in ddr register: bit x corre- sponding to pin x of the port. the same corre- spondence is used for the dr register. table 8. i/o pin functions 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. notes : 1. all the inputs are triggered by a schmitt trigger. 2. when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is configured as an output. interrupt function when an external interrupt function of an i/o pin, is enabled using the itfre registers, an event on this i/o can generate an external interrupt request to the cpu. the interrupt sensitivity is programma- ble, the options are given in the description of the itrfre interrupt registers. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt sour ce, this is logically an- ded and inverted. for this reason, if an event oc- curs on one of the interrupt pins, it masks the other ones. 9.2.2 output mode the pin is configured in output mode by setting the corresponding ddr register bit (see table 7). in this mode, writing ?0? or ?1? to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. 9.2.3 alternate functions digital alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the alternate peripheral input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : alternate functions of peripherals must must not be activated when the external interrupts are enabled on the same pin, in order to avoid generating spurious interrupts. ddr mode 0 input 1 output
st7262 33/139 i/o ports (cont?d) analog alternate functions when the pin is used as an adc input, the i/o must be configured as input. the analog multiplex- er (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.2.4 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr register and spe- cific features of the i/o port such as adc input or true open drain.
st7262 34/139 i/o ports (cont?d) 9.2.5 port a table 9. port a description figure 26. pa[7:0] configuration port a i/o alternate function input* output signal condition pa0 floating push-pull usboe usboe = 1 (misc) it1 schmitt triggered input it1e = 1 (itrfre1) ain0 (adc) cs[2:0] = 000 (adccsr) pa1 floating push-pull it2 schmitt triggered input it2e = 1 (itrfre1) ain1 (adc) cs[2:0] = 001 (adccsr) pa2 floating push-pull it3 schmitt triggered input it3e = 1 (itrfre1) ain2 (adc) cs[2:0] = 010 (adccsr) pa3 floating push-pull it4 schmitt triggered input it4e = 1 (itrfre1) ain3 (adc) cs[2:0] = 011 (adccsr) pa4 floating push-pull ain4 (adc) cs[2:0] = 100 (adccsr) pa5 floating push-pull ain5 (adc) cs[2:0] = 101 (adccsr) pa6 floating push-pull ain6 (adc) cs[2:0] = 110 (adccsr) pa7 floating push-pull ain7 (adc) cs[2:0] = 111 (adccsr) *reset state dr ddr latch latch dr sel ddr sel v dd pa d analog switch analog enable (adc) alternate enable alternate enable digital enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 v ss data bus common analog rail v dd diodes
st7262 35/139 i/o ports (cont?d) 9.2.6 port b table 10. port b description figure 27. port b and port c [7:2] configuration port b i/o alternate function input* output signal condition pb0 floating push-pull (high sink) mco (main clock output) mco = 1 (miscr) pb1 floating push-pull (high sink) rdi sci enabled pb2 floating push-pull (high sink) tdo te = 1 (scicr2) pb3 floating push-pull (high sink) artclk excl = 1 (artcsr) pb4 floating push-pull (high sink) artic1 art timer enabled it5 schmitt triggered input it5e = 1 (itrfre1) pb5 floating push-pull (high sink) artic2 art timer enabled it6 schmitt triggered input it6e = 1 (itrfre1) pb6 floating push-pull (high sink) pwm1 oe0 = 1 (pwmcr) it7 schmitt triggered input it7e = 1 (itrfre1) pb7 floating push-pull (high sink) pwm2 oe1 = 1 (pwmcr) it8 schmitt triggered input it8e = 1 (itrfre1) *reset state dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus pull-up* * pull-up on port c [7:2] only
st7262 36/139 i/o ports (cont?d) 9.2.7 port c table 11. port c description figure 28. port c[1:0] configuration port c i/o alternate function input* output signal condition pc0 floating true open drain pc1 floating true open drain pc2 with pull-up push-pull it9 schmitt triggered input it9e = 1 (itrfre2) pc3 with pull-up push-pull sck spi enabled it10 schmitt triggered input it10e = 1 (itrfre2) pc4 with pull-up push-pull ss spi enabled it11 schmitt triggered input it11e = 1 (itrfre2) pc5 with pull-up push-pull miso spi enabled it12 schmitt triggered input it12e = 1 (itrfre2) pc6 with pull-up push-pull mosi spi enabled pc7 with pull-up push-pull *reset state dr ddr latch latch dr sel ddr sel pa d alternate enable alternate enable alternate output n-buffer 1 0 1 0 cmos schmitt trigger v ss diodes data bus
st7262 37/139 i/o ports (cont?d) 9.2.8 port d table 12. port d description figure 29. port d configuration port d i/o alternate function input* output signal condition pd0 with pull-up push-pull pd1 with pull-up push-pull pd2 with pull-up push-pull pd3 with pull-up push-pull pd4 with pull-up push-pull pd5 with pull-up push-pull pd6 with pull-up push-pull *reset state dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd data bus diodes
st7262 38/139 i/o ports (cont?d) 9.2.9 register description data register (dr) port x data register pxdr with x = a, b, c or d. read/write reset value: 0000 0000 (00h) bits 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c or d. read/write reset value: 0000 0000 (00h) bits 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0
st7262 39/139 i/o ports (cont?d) table 13. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h pbdr msb lsb 0003h pbddr 0004h pcdr msb lsb 0005h pcddr 0006h pddr msb lsb 0007h pdddr
st7262 40/139 9.3 miscellaneous register miscellaneous register read write reset value - 0000 0000 (00h) bits 7:4 = reserved bits 3:2 = sms[1:0] slow mode selection these bits select the slow mode frequency (de- pending on the oscillator frequency configured by option byte). bit 1 = usboe usb output enable 0: pa0 port free for general purpose i/o 1: usboe alternate function enabled. the usb output enable signal is output on the pa0 port (at ?1? when the st7 usb is transmitting data). bit 0 = mco main clock out 0: pb0 port free for general purpose i/o 1: mco alternate function enabled (f cpu output on pb0 i/o port) 70 ----sms1sms0 us- boe mco osc12/6 sms1 sms0 slow mode frequency (mhz.) f osc = 6 mhz. 00 4 01 2 10 1 11 0.5 f osc = 12 mhz. 00 8 01 4 10 2 11 1
st7262 41/139 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter?s contents before the t6 bit be- comes cleared. 10.1.2 main features programmable free-running downcounter (64 increments of 65536 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 65,536 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 30s. the application program mu st write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down even if the watchdog is di- abled the value to be stored in the cr register must be between ffh and c0h (see table 14 ): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme- diate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 14.watchdog timing (f cpu = 8 mhz) figure 30. watchdog block diagram cr register initial value wdg timeout period (ms) max ffh 524.288 min c0h 8.192 reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 65536 t1 t2 t3 t4 t5
st7262 42/139 watchdog timer (cont?d) 10.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 10.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 10.1.6 low power modes wait instruction no effect on watchdog. halt instruction halt mode can be used when the watchdog is en- abled. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 514 cpu clocks. in the case of the software watchdog option, if a reset is gen- erated, the wdg is disabled (reset state). recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as input before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 10.1.7 interrupts none. 10.1.8 register desc4ription control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 15. watchdog timer register map and reset values 70 wdga t6 t5 t4 t3 t2 t1 t0 address (hex.) register label 76543210 0dh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
st7262 43/139 10.2 pwm auto-reload timer (art) 10.2.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with com pare/capture capabilities and of a 7-bit prescaler clock source. these resources allow five possible operating modes: ? generation of up to 2 independent pwm signals ? output compare and time base interrupt ? up to two input capture functions ? external event detector ? up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 31. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (artcar register) artarr register articrx register load opx polarity control oex pwmcr mux f cpu pwmdcrx register load f counter artclk f ext articx icfx icsx articcsr load icx interrupt iciex input capture control
st7262 44/139 pwm auto-reload timer (cont?d) 10.2.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). counter clock and prescaler the counter clock fr equency is given by: f counter = f input / 2 cc[2:0] the timer counter?s input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescal- er can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input = f cpu . the counter can be initialized by: ? writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr reg- ister. ? writing to the artcar counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the pre scaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 32. output compare control counter fdh feh ffh fdh feh ffh fdh feh artarr=fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx
st7262 45/139 pwm auto-reload timer (cont?d) independent pwm signal generation this mode allows up to two pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be no ted that the rel oad values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr reg- ister. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note : to get the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. figure 33. pwm auto-reload timer function duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter
st7262 46/139 pwm auto-reload timer (cont?d) figure 34. pwm signal from 0% to 100% duty cycle counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr=fdh f counter
st7262 47/139 pwm auto-reload timer (cont?d) output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generat- ed if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be re- set by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr when entering halt mode while f ext is selected, all the timer control registers are frozen but the counter continues to increment. if the oie bit is set, the next overflow of the counte r will generate an interrupt which wakes up the mcu. caution: if halt mode is used in the application, prior to executing the halt instruction, the coun- ter must be disabled by clearing the tce bit in the artcsr register to avoid spurious counter incre- ments. figure 35. external event detector example (3 counts) counter t fdh feh ffh fdh ovf artcsr read interrupt artarr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 artcsr read
st7262 48/139 pwm auto-reload timer (cont?d) input capture function this mode allows the measurement of external signal pulse widths through icrx registers. each input capture can generate an interrupt inde- pendently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status regis- ter (iccsr). these input capture interrupts are enabled through the ciex bits of the iccsr register. the active transition (falling or rising edge) is soft- ware programmable through the csx bits of the iccsr register. the read only input capture registers (icrx) are used to latch the auto-reload counter value when a transition is detected on the articx pin (cfx bit set in iccsr register). after fetching the interrupt vector, the cfx flags can be read to identify the in- terrupt source. note : after a capture detection, data transfer in the icrx register is inhibited until the articcsr register is read (clearing the cfx bit). the timer interrupt remain s pending while the cfx flag is set when the interr upt is enabled (ciex bit set). this means, the articcsr register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun- ter cycle time (1/f counter ). during halt mode, input capture is inhibited (the icrx is never re-loaded) and only the external in- terrupt capability can be used. external interrupt capability this mode allows the inpu t capture capabilities to be used as external interrupt sources. the edge sensitivity of the external interrupts is programmable (csx bit of iccsr register) and they are independently enabled through ciex bits of the iccsr register. after fetching the interrupt vector, the cfx flags can be read to identify the in- terrupt source. the interrupts are synchronized on the counter clock rising edge ( figure 36 ). during halt mode, the external interrupts can still be used to wake up the micro (if ciex bit is set). figure 36. art external interrupt figure 37. input capture timing diagram articx pin cfx flag t f counter interrupt counter t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt
st7262 49/139 pwm auto-reload timer (cont?d) 10.2.3 register description control / status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of arr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the csr register. it indicates the transition of the counter from ffh to the arr value . 0: new transition not yet reached 1: transition reached counter access register (car) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the car register is used to read or write the auto-reload counter ?on the fly? (while it is counting). auto-reload register (arr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: ? adjusting the pwm frequency ? setting the pwm duty cycle resolution pwm frequency vs. resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 70 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 arr value resolution f pwm min max 0 8-bit ~0.244-khz 31.25-khz [ 0..127 ] > 7-bit ~0.244-khz 62.5-khz [ 128..191 ] > 6-bit ~0.488-khz 125-khz [ 192..223 ] > 5-bit ~0.977-khz 250-khz [ 224..239 ] > 4-bit ~1.953-khz 500-khz
st7262 50/139 pwm auto-reload timer (cont?d) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved. bit 5:4 = oe[1:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:2 = reserved. bit 1:0 = op[1:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the two pwm output signals. notes : ? when an opx bit is modified, the pwmx output signal polarity is immediately reversed. ? if dcrx=ffh then the ou tput level is always 0. ? if dcrx=00h then the output level is always 1. duty cycle registers (dcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a dcrx register is associated with the ocrx reg- ister of each pwm channel to determine the sec- ond edge location of the pwm signal (the first edge location is common to all channels and given by the arr register). these dcr registers allow the duty cycle to be set independently for each pwm channel. 70 00oe1oe000op1op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0
st7262 51/139 pwm auto-reload timer (cont?d) input capture control / status register (articcsr) read/write (except bits 1:0 read and clear) reset value: 0000 0000 (00h) bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corre- sponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel inter- rupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware when a capture oc- curs and cleared by hardware when software reads the articcsr register. each cfx bit indi- cates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occured on channel x. input capture registers (articrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hard- ware. an articrx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. 70 0 0 cs2 cs1 cie2 cie1 cf2 cf1 70 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0
st7262 52/139 pwm auto-reload timer (cont?d) table 16. pwm auto-reload timer register map and reset values address (hex.) register label 7654321 0 0014h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0015h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0016h pwmcr reset value 0 0 0 0 oe1 0 oe0 0 0 0 0 0 op1 0 op0 0 0017h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 oie 0 ovf 0 0018h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 0019h artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 001ah articcsr reset value 0 0 cs2 0 cs1 0 cie2 0 cie1 0 cf2 0 cf1 0 001bh articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 001ch articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0
st7262 53/139 10.3 timebase unit (tbu) 10.3.1 introduction the timebase unit (tbu) can be used to generate periodic interrupts. 10.3.2 main features 8-bit upcounter programmable prescaler period between interrupts: max. 8.1ms (at 8 mhz f cpu ) maskable interrupt cascadable with pwm/art timer 10.3.3 functional description the tbu operates as a free-running upcounter. when the tcen bit in the tbucsr register is set by software, counting starts at the current value of the tbucv register. the tb ucv register is incre- mented at the clock rate output from the prescaler selected by programming the pr[2:0] bits in the tbucsr register. when the counter rolls over from ffh to 00h, the ovf bit is set and an interrupt request is generat- ed if ite is set. the user can write a value at any time in the tbucv register. if the cascading option is selected (cas bit=1 in the tbucsr register), the tbu and the the art timer counters act together as a 16-bit counter. in this case, the tbucv register is the high order byte, the art counter (artcar register) is the low order byte. counting is clocked by the art timer clock (refer to the description of the art timer artcsr register). 10.3.4 programming example in this example, timer is required to generate an in- terrupt after a delay of 1 ms. assuming that f cpu is 8 mhz and a prescaler divi- sion factor of 256 will be programmed using the pr[2:0] bits in the tbucsr register, 1 ms = 32 tbu timer ticks. in this case, the initial value to be loaded in the tbucv must be (256-32) = 224 (e0h). ld a, e0h ld tbucv, a ; initialize counter value ld a 1fh ; ld tbucsr, a ; prescaler factor = 256, ; interrupt enable, ; tbu enable figure 38. tbu block diagram tbu 8-bit upcounter (tbucv register) interrupt request tbu prescaler f cpu tbucsr register pr1 pr0 pr2 tcen ite ovf msb lsb art pwm timer 8-bit counter msb lsb cas 0 1 tbu art timer carry bit 0
st7262 54/139 timebase unit (cont?d) 10.3.5 low power modes 10.3.6 interrupts note : the ovf interrupt event is connected to an interrupt vector (see interrupts chapter). it generates an interrupt if the ite bit is set in the tbucsr register and the i-bit in the cc register is reset (rim instruction). 10.3.7 register description tbu counter value register (tbucv) read/write reset value: 0000 0000 (00h) bit 7:0 = cv[7:0] counter value this register contains the 8-bit counter value which can be read and written anytime by soft- ware. it is continuously incremented by hardware if tcen=1. tbu control/status register (tbucsr) read/write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0 . bit 6 = cas cascading enable this bit is set and cleared by software. it is used to cascade the tbu and the pwm/art timers. 0: cascading disabled 1: cascading enabled bit 5 = ovf overflow flag this bit is set only by hardware, when the counter value rolls over from ffh to 00h. it is cleared by software reading the tbucsr register. writing to this bit does not change the bit value. 0: no overflow 1: counter overflow bit 4 = ite interrupt enabled. this bit is set and cleared by software. 0: overflow interrupt disabled 1: overflow interrupt enabled. an interrupt request is generated when ovf=1. bit 3 = tcen tbu enable. this bit is set and cleared by software. 0: tbu counter is frozen and the prescaler is reset. 1: tbu counter and prescaler running. bit 2:0 = pr[2:0] prescaler selection these bits are set and cleared by software to se- lect the prescaling factor. mode description wait no effect on tbu halt tbu halted. interrupt event event flag enable control bit exit from wait exit from halt counter over- flow event ovf ite yes no 70 cv7cv6cv5cv4cv3cv2cv1cv0 70 0 cas ovf ite tcen pr2 pr1 pr0 pr2 pr1 pr0 prescaler division factor 000 2 001 4 010 8 011 16 100 32 101 64 1 1 0 128 1 1 1 256
st7262 55/139 timebase unit (cont?d) table 17. tbu register map and reset values address (hex.) register label 76543210 0036h tbucv reset value cv7 0 cv6 0 cv5 0 cv4 0 cv3 0 cv2 0 cv1 0 cv0 0 0037h tbusr reset value - 0 cas 0 ovf 0 ite 0 tcen 0 pr2 0 pr1 0 pr0 0
st7262 56/139 10.4 serial peripheral interface (spi) 10.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface can not be a master in a multi-master system. 10.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 general description figure 39 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 3 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master mcu. figure 39. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st7262 57/139 serial peripheral interface (cont?d) 10.4.3.1 functional description a basic example of inte rconnections between a single master and a sing le slave is illustrated in figure 40 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is alwa ys initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this imp lies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 43 ) but master and slave must be programmed with the same timing mode. figure 40. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software
st7262 58/139 serial peripheral interface (cont?d) 10.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 42 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 41 ): if cpha=1 (data latched on 2nd clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 10.4.5.3 ). figure 41. generic ss timing diagram figure 42. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin
st7262 59/139 serial peripheral interface (cont?d) 10.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following two steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into ac- count) : 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 43 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 10.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 10.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 43 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 10.4.3.2 and figure 41 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 10.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 10.4.5.2 ).
st7262 60/139 serial peripheral interface (cont?d) 10.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 43 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 43 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 43. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0)
st7262 61/139 serial peripheral interface (cont?d) 10.4.5 error flags 10.4.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflic t and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 10.4.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 10.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 10.4.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 44 ). figure 44. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result
st7262 62/139 serial peripheral interface (cont?d) 10.4.5.4 single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 45 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. figure 45. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st7262 63/139 serial peripheral interface (cont?d) 10.4.6 low power modes 10.4.6.1 using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is run- ning (interrupt vector fetch). if multiple data trans- fers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selec- tion is configured as external (see section 10.4.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 10.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the mcu is woken up by an interrupt with ?exit from halt mode? ca- pability. the data received is subsequently read from the spidr r egister when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine t hat woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no
st7262 64/139 serial peripheral interface (cont?d) 10.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1, modf=1 or ovr=1 in the spicsr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.4.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initia lly connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 18 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.4.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 18. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 spr2 spr1 spr0 serial clock (f cpu = 8mhz) serial clock (f cpu = 4mhz) sck 100 f cpu /4 f cpu /2 2 mhz 000 f cpu /8 f cpu /4 1 mhz 001 f cpu /16 f cpu /8 0.5 mhz 110 f cpu /32 f cpu /16 0.25 mhz 010 f cpu /64 f cpu /32 125 khz 011 f cpu /128 f cpu /64 62.5 khz
st7262 65/139 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr regist er. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 44 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 10.4.5.2 ). an interrupt is generated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 10.4.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 10.4.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 39 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0
st7262 66/139 table 19. spi register map and reset values address (hex.) register label 76543210 0011h spidr reset value msb xxxxxxx lsb x 0012h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0013h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
st7262 67/139 10.5 serial communications interface (sci) 10.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 10.5.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ? frame error ? parity error five interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 10.5.3 general description the interface is externally connected to another device by two pins (see figure 47 ): ? tdo: transmit data output. when the transmit- ter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: ? a conventional type for commonly-used baud rates, ? an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.
st7262 68/139 serial communications interface (cont?d) figure 46. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2
st7262 69/139 serial communications interface (cont?d) 10.5.4 functional description the block diagram of the serial control interface, is shown in figure 46 . it contains 6 dedicated reg- isters: ? two control registers (scicr1 & scicr2) ? a status register (scisr) ? a baud rate register (scibrr) ? an extended prescaler receiver register (scier- pr) ? an extended prescaler transmitter register (sci- etpr) refer to the register descriptions in section 10.5.7 for the definitions of each bit. 10.5.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 46 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 47. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame
st7262 70/139 serial communications interface (cont?d) 10.5.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 46 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit) the tc bit is set and an interrupt is gener- ated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 47 ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr.
st7262 71/139 serial communications interface (cont?d) 10.5.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 46 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared. when a overrun error occurs: ? the or bit is set. ? the rdr content will not be lost. ? the shift register will be overwritten. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge de- tection as well as three valid samples. when noise is detected in a frame: ? the nf flag is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read op- eration followed by a scidr register read opera- tion. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the applica- tion software when the first valid byte is received. see also section 10.5.4.10 .
st7262 72/139 serial communications interface (cont?d) figure 48. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
st7262 73/139 serial communications interface (cont?d) framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. 10.5.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 10.5.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry stan dard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 48 . the output clock rate sent to the transmitter or to the receiver will be the ou tput from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) 10.5.4.6 receiver muting and wake-up feature in multiprocessor configurat ions it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interr upts are inhibited. a muted receiver may be awakened by one of the following two ways: ? by idle line detection if the wake bit is reset, ? by address mark detectio n if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution : in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu=1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit will be set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu
st7262 74/139 serial communications interface (cont?d) 10.5.4.7 parity control parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in table 20 . table 20. frame formats legend: sb = start bit, stb = stop bit, pb = parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pie is set in the scicr1 register. 10.5.4.8 sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detec- tion, all the three samples should have the same value otherwise the noise flag (nf) is set. for ex- ample: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be ?1?, but the noise flag bit is be set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the de- sired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal sampling clock of the microcon- troller samples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32s & 36s respectively (the first sample starting ideally at 0s). but if the falling edge of the internal clock oc- curs just before the pin value changes, the sam- ples would then be out of sync by ~4us. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchroniza- tion with the internal sampling clock). m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb |
st7262 75/139 serial communications interface (cont?d) 10.5.4.9 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error (local oscillator error of the tr ansmitter or the trans- mitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantisa- tion of the receiver. ?d rec : deviation of the lo cal oscillator of the receiver: this deviation can occur during the reception of one complete sci message as- suming that the deviation has been compen- sated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% 10.5.4.10 noise error causes see also description of noise error in section 10.5.4.3 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not detected. a falling edge is considered to be valid if the 3 consecu- tive samples before t he falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit re- ception if the following condition occurs: ? during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set. figure 49. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16
st7262 76/139 serial communications interface (cont?d) 10.5.5 low power modes 10.5.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corre- sponding enable control bi t is set and the inter- rupt mask in the cc regist er is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit- ting/receiving until halt mode is exit- ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no
st7262 77/139 serial communications interface (cont?d) 10.5.7 register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data will not be transfer red to the shift reg- ister unless the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardwar e when transmission of a frame containing data is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift re gister will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be tr ansferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error 70 tdre tc rdrf idle or nf fe pe
st7262 78/139 serial communications interface (cont?d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected afte r the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled. 70 r8 t8 scid m wake pce ps pie
st7262 79/139 serial communications interface (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wakeup by idle line detection. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter will send a break word at the end of the current word. 70 tie tcie rie ilie te re rwu sbk
st7262 80/139 serial communications interface (cont?d) data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 46 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 46 ). baud rate register (scibrr) read/write reset value: 0000 0000 (00h) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate cl ock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1
st7262 81/139 serial communications interface (cont?d) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 48 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 48 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 21. baudrate selection 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr)= 1, pr=1 14400 ~14285.71
st7262 82/139 serial communications interface (cont?d) table 22. sci register map and reset values address (hex.) register name 76543210 1d scierpr reset value erpr7 0 erpr6 0 erpr5 0 erpr4 0 erpr3 0 erpr2 0 erpr1 0 erpr0 0 1e scietpr reset value etpr7 0 etpr6 0 etpr5 0 etpr4 0 etpr3 0 etpr2 0 etpr1 0 etpr0 0 20 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 21 scidr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 22 scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 23 scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 24 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0
st7262 83/139 10.6 usb interface (usb) 10.6.1 introduction the usb interface implements a low-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and dma. no external components are needed apart from the external pull-up on usbdm for low speed recognition by the usb host. the use of dma architecture allows the endpoint definition to be completely flexible. endpoints can be config- ured by software as in or out. 10.6.2 main features usb specification version 1.1 compliant supports low-speed usb protocol two or three endpoints (including default one) depending on the device (see device feature list and register map) crc generation/checking, nrzi encoding/ decoding and bit-stuffing usb suspend/resume operations dma data transfers on-chip 3.3v regulator on-chip usb transceiver 10.6.3 functional description the block diagram in figure 50 , gives an overview of the usb interface hardware. for general information on the usb, refer to the ?universal serial bus specifications? document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. dma when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place, using dma. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 50. usb block diagram cpu memory transceiver 3.3v voltage regulator sie endpoint dma interrupt address, and interrupts usbdm usbdp usbvcc 6 mhz registers registers data buses usbgnd
st7262 84/139 usb interface (cont?d) 10.6.4 register description dma address register (dmar) read / write reset value: undefined bits 7:0= da[15:8] dma address bits 15-8. software must write the start address of the dma memory area whose most significant bits are given by da15-da6. the remaining 6 address bits are set by hardware. see the description of the idr register and figure 51 . interrupt/dma register (idr) read / write reset value: xxxx 0000 (x0h) bits 7:6 = da[7:6] dma address bits 7-6. software must reset these bits. see the descrip- tion of the dmar register and figure 51 . bits 5:4 = ep[1:0] endpoint number (read-only). these bits identify the endpoint which required at- tention. 00: endpoint 0 01: endpoint 1 10: endpoint 2 when a ctr interrupt occurs (see register istr) the software should read the ep bits to identify the endpoint which has sent or received a packet. bits 3:0 = cnt[3:0] byte count (read only). this field shows how many data bytes have been received during the last data reception. note: not valid for data transmission. figure 51. dma buffers 70 da15 da14 da13 da12 da11 da10 da9 da8 70 da7 da6 ep1 ep0 cnt3 cnt2 cnt1 cnt0 endpoint 0 rx endpoint 0 tx endpoint 2 rx endpoint 1 tx 000000 000111 001000 001111 010000 010111 011000 011111 da15-6,000000 endpoint 1 rx endpoint 2 tx 100000 100111 101000 101111
st7262 85/139 usb interface (cont?d) pid register (pidr) read only reset value: xx00 0000 (x0h) bits 7:6 = tp[3:2] token pid bits 3 & 2 . usb token pids are encoded in four bits. tp[3:2] correspond to the variable token pid bits 3 & 2. note: pid bits 1 & 0 have a fixed value of 01. when a ctr interrupt occurs (see register istr) the software should read the tp3 and tp2 bits to retrieve the pid name of the token received. the usb standard defines tp bits as: bits 5:3 reserved. forced by hardware to 0. bit 2 = rx_sez received single-ended zero this bit indicates the status of the rx_sez trans- ceiver output. 0: no se0 (single-ended zero) state 1: usb lines are in se0 (single-ended zero) state bit 1 = rxd received data 0: no k-state 1: usb lines are in k-state this bit indicates the status of the rxd transceiver output (differential receiver output). note: if the environment is noisy, the rx_sez and rxd bits can be used to secure the application. by interpreting the status, software can distinguish a valid end suspend event from a spurious wake-up due to noise on the external usb line. a valid end suspend is followed by a resume or reset se- quence. a resume is indicated by rxd=1, a re- set is indicated by rx_sez=1. bit 0 = reserved. forced by hardware to 0. interrupt status register (istr) read / write reset value: 0000 0000 (00h) when an interrupt occurs these bits are set by hardware. software must read them to determine the interrupt type and clear them after servicing. note: these bits cannot be set by software. bit 7 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb bus. the suspend request check is active immedi- ately after each usb reset event and its disabled by hardware when suspend mode is forced (fsusp bit of ctlr register) until the end of resume sequence. bit 6 = dovr dma over/underrun . this bit is set by hardware if the st7 processor can?t answer a dma request in time. 0: no over/underrun detected 1: over/underrun detected bit 5 = ctr correct transfer. this bit is set by hardware when a correct transfer operation is per- formed. the type of transfer can be determined by looking at bits tp3-tp2 in register pidr. the end- point on which the transfer was made is identified by bits ep1-ep0 in register idr. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 4 = err error. this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing or nonstandard framing error detected 70 tp3 tp2 0 0 0 rx_ sez rxd 0 tp3 tp2 pid name 00 out 10 in 11 setup 70 susp dovr ctr err iovr esusp reset sof
st7262 86/139 usb interface (cont?d) bit 3 = iovr interrupt overrun. this bit is set when hardware tries to set err, or sof before they have been cleared by software. 0: no overrun detected 1: overrun detected bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0ra, ep0rb, ep1ra, ep1rb, ep2ra and ep2rb registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardwa re when a low-speed sof indication (keep-alive strobe) is seen on the usb bus. it is also issued at the end of a resume se- quence. 0: no sof signal detected 1: sof signal detected note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and , xor.. interrupt mask register (imr) read / write reset value: 0000 0000 (00h) bits 7:0 = these bits are mask bits for all interrupt condition bits included in the istr. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the corresponding bit description in istr. control register (ctlr) read / write reset value: 0000 0110 (06h) bits 7:4 = reserved. forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be halted allowing at least 600 ns before issuing the halt instruction. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset state until software clears this bit, at whic h point a ?usb-reset? in- terrupt will be gen erated if enabled. 70 sus pm dov rm ctr m err m iovr m esu spm res etm sof m 70 0 0 0 0 resume pdwn fsusp fres
st7262 87/139 usb interface (cont?d) device address register (daddr) read / write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received from the usb bus or forced through bit fres in the ctlr register. endpoint n register a (epnra) read / write reset value: 0000 xxxx (0xh) these registers ( ep0ra , ep1ra and ep2ra ) are used for controlling data transmission. they are also reset by the usb bus reset. note : endpoint 2 and the ep2ra register are not available on some devices (see device feature list and register map). bit 7 = st_out status out. this bit is set by software to indicate that a status out packet is expected: in this case, all nonzero out data transfers on the endpoint are stalled instead of being acked. when st_out is reset, out transactions can have any number of bytes, as needed. bit 6 = dtog_tx data toggle, for transmission transfers. it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware at the re- ception of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx (see epnrb) are normally updated by hardware, at the receipt of a relevant pid. they can be also written by software. bits 5:4 = stat_tx[1:0] status bits, for transmis- sion transfers. these bits contain the information about the end- point status, whic h are listed below: these bits are written by software. hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) related to a in or setup transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. bits 3:0 = tbc[3:0] transmit byte count for end- point n. before transmissi on, after filling the transmit buff- er, software must write in the tbc field the trans- mit packet size expressed in bytes (in the range 0- 8). warning: any value outside the range 0-8 will- induce undesired effects (such as continuous data transmission). 70 0 add6 add5 add4 add3 add2 add1 add0 70 st_ out dtog _tx stat _tx1 stat _tx0 tbc 3 tbc 2 tbc 1 tbc 0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission.
st7262 88/139 usb interface (cont?d) endpoint n register b (epnrb) read / write reset value: 0000 xxxx (0xh) these registers ( ep1rb and ep2rb ) are used for controlling data reception on endpoints 1 and 2. they are also reset by the usb bus reset. note : endpoint 2 and the ep2rb register are not available on some devices (see device feature list and register map). bit 7 = ctrl control. this bit should be 0. note: if this bit is 1, the endpoint is a control end- point. (endpoint 0 is always a control endpoint, but it is possible to have more than one control end- point). bit 6 = dtog_rx data toggle, for reception trans- fers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by ha rdware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packet?s data pid matches the receiver sequence bit. bits 5:4 = stat_rx [1:0] status bits, for reception transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) related to an out or set- up transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. bits 3:0 = ea[3:0] endpoint address . software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. usually ep1rb contains ?0001? and ep2rb contains ?0010?. endpoint 0 register b (ep0rb) read / write reset value: 1000 0000 (80h) this register is used fo r controlling data reception on endpoint 0. it is also reset by the usb bus re- set. bit 7 = forced by hardware to 1. bits 6:4 = refer to the epnrb register for a de- scription of these bits. bits 3:0 = forced by hardware to 0. 70 ctrl dtog _rx stat _rx1 stat _rx0 ea3 ea2 ea1 ea0 stat_rx1 stat_rx0 meaning 00 disabled : reception transfers cannot be exe- cuted. 01 stall: the endpoint is stalled and all reception requests result in a stall handshake. 10 nak : the endpoint is na- ked and all reception re- quests result in a nak handshake. 11 valid : this endpoint is enabled for reception. 70 1 dtog rx stat rx1 stat rx0 0000 stat_rx1 stat_rx0 meaning
89/139 usb interface (cont?d) 10.6.5 programming considerations the interaction between the usb interface and the application program is described below. apart from system reset, action is always initiated by the usb interface, driven by one of the usb events associated with the interrupt status register (is- tr) bits. 10.6.5.1 initializing the registers at system reset, the softwa re must initialize all reg- isters to enable the usb interface to properly gen- erate interrupts and dma requests. 1. initialize the dmar, idr, and imr registers (choice of enabled interrupts, address of dma buffers). refer the parag raph titled initializing the dma buffers. 2. initialize the ep0ra and ep0rb registers to enable accesses to address 0 and endpoint 0 to support usb enumeration. refer to the para- graph titled endpoint initialization. 3. when addresses are received through this channel, update the content of the daddr. 4. if needed, write the endpoint numbers in the ea fields in the ep1rb and ep2rb register. 10.6.5.2 initializing dma buffers the dma buffers are a contiguous zone of memo- ry whose maximum size is 48 bytes. they can be placed anywhere in the memory space to enable the reception of messages. the 10 most signifi- cant bits of the start of this memory area are spec- ified by bits da15-da6 in registers dmar and idr, the remaining bits are 0. the memory map is shown in figure 51 . each buffer is filled starting from the bottom (last 3 address bits=000) up. 10.6.5.3 endpoint initialization to be ready to receive: set stat_rx to valid (11b) in ep0rb to enable reception. to be ready to transmit: 1. write the data in the dma transmit buffer. 2. in register epnra, specify the number of bytes to be transmitted in the tbc field 3. enable the endpoint by setting the stat_tx bits to valid (11b) in epnra. note: once transmission and/or reception are en- abled, registers epnra and/or epnrb (respec- tively) must not be modified by software, as the hardware can change their value on the fly. when the operation is completed, they can be ac- cessed again to enable a new operation. 10.6.5.4 interrupt handling start of frame (sof) the interrupt service routine may monitor the sof events for a 1 ms synchronization event to the usb bus. this interrupt is generated at the end of a resume sequence and can also be used to de- tect this event. usb reset (reset) when this event occurs, the daddr register is re- set, and communication is disabled in all endpoint registers (the usb interfac e will not resp ond to any packet). software is re sponsible for reenabling endpoint 0 within 10 ms of the end of reset. to do this, set the stat_rx bits in the ep0rb register to valid. suspend (susp) the cpu is warned about the lack of bus activity for more than 3 ms, which is a suspend request. the software should set the usb interface to sus- pend mode and execute an st7 halt instruction to meet the usb-specified power constraints. end suspend (esusp) the cpu is alerted by activity on the usb, which causes an esusp interrupt. the st7 automatical- ly terminates halt mode. correct transfer (ctr) 1. when this event occurs, the hardware automat- ically sets the stat_tx or stat_rx to nak. note: every valid endpoint is naked until soft- ware clears the ctr bit in the istr register, independently of the endpoint number addressed by the transfer which generated the ctr interrupt. note: if the event triggering the ctr interrupt is a setup transaction, both stat_tx and stat_rx are set to nak. 2. read the pidr to obtain the token and the idr to get the endpoint number related to the last transfer. note: when a ctr interrupt occurs, the tp3- tp2 bits in the pidr register and ep1-ep0 bits in the idr register stay unchanged until the ctr bit in the istr register is cleared. 3. clear the ctr bit in the istr register.
90/139 usb interface (cont?d) table 23. usb register map and reset values address (hex.) register name 7 6 5 4 3210 25 pidr reset value tp3 x tp2 x 0 0 0 0 0 0 rx_sez 0 rxd 0 0 0 26 dmar reset value da15 x da14 x da13 x da12 x da11 x da10 x da9 x da8 x 27 idr reset value da7 x da6 x ep1 x ep0 x cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 istr reset value susp 0 dovr 0 ctr 0 err 0 iovr 0 esusp 0 reset 0 sof 0 29 imr reset value suspm 0 dovrm 0 ctrm 0 errm 0 iovrm 0 esuspm 0 resetm 0 sofm 0 2a ctlr reset value 0 0 0 0 0 0 0 0 resume 0 pdwn 1 fsusp 1 fres 0 2b daddr reset value 0 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2c ep0ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2d ep0rb reset value 1 1 dtog_rx 0 stat_rx1 0 stat_rx0 0 0 0 0 0 0 0 0 0 2e ep1ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2f ep1rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x 30 ep2ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 31 ep2rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x
91/139 10.7 10-bit a/d converter (adc) 10.7.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.7.2 main features 10-bit conversion up to 8 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag continuous or one-shot mode on/off bit (to reduce consumption) the block diagram is shown in figure 52 . 10.7.3 functional description 10.7.3.1 analog power supply depending on the mcu pin count, the package may feature separate v dda and v ssa analog pow- er supply pins. these pins supply power to the a/d converter cell and function as the high and low ref- erence voltages for the conversion. in smaller packages v dda and v ssa pins are not available and the analog supply and reference pads are in- ternally bonded to the v dd and v ss pins. separation of the digital and analog power pins al- low board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 10.7.3.2 pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to sh ield the the noise-sensi- tive, analog physical interface from noise-generat- ing cmos logic signals. ? use separate digital and analog planes. the an- alog ground plane should be connected to the digital ground plane via a single point on the pcb. the analog power plane should be con- nected to the digital power plane via an rc net- work. ? filter power to the analog power planes. the best solution is to connect a 0.1f capacitor, with good high frequency characteristics, between v dda and v ssa and place it as close as possible to the v dda and v ssa pins and connect the ana- log and digital power supplies in a star network. do not use a resistor, as v dda is used as a refer- ence voltage by the a/d converter and resist- ance would cause a voltage drop and a loss of accuracy. ? properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signal from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs on the same i/o port as the a/d input being convert- ed. 10.7.3.3 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the adcdrmsb register and 03h in the adcdrlsb register (without overflow indi- cation). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrmsb and adcdrlsb registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrmsb and adcdrlsb registers. the accuracy of the con- version is described in the electrical characteris- tics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.
92/139 10-bit a/d converter (adc) (cont?d) 10.7.3.4 a/d conversion conversion can be performed in one-shot or con- tinuous mode. continuous mode is typically used for monitoring a single channel. one-shot mode should be used when the application requires in- puts from several channels. adc configuration the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[2:0] bits to assign the analog channel to convert. adc one-shot conversion mode in the adccsr register: 1.set the one shot bit to put the a/d converter in one shot mode. 2.set the adon bit to enable the a/d converter and to start the conversion. the eoc bit is kept low by hardware during the conversion. note: changing the a/d channel during conver- sion will stop the current conversion and start con- version of the newly selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? an interrupt request is generated if the ite bit is set. ? the adon bit is reset by hardware. ? the result is in the adcdr registers. to read the 10 bits, perform the following steps: 1. wait for interrupt or poll the eoc bit 2. read adcdrlsb 3. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. figure 52. adc block diagram cs2 cs1 eoc speed adon ite cs0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrmsb 3 div 2 f adc f cpu d1 d0 adcdrlsb div 4 0 1 eoc interrupt 00 0000 one shot
93/139 10-bit a/d converter (adc) (cont?d) to read only 8 bits, perform the following steps: 1. wait for interrupt or poll the eoc bit 2. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. to start another conversion, user should set the adon bit once again. adc continuous conversion mode in the adccsr register: 1.reset the one shot bit to put the a/d con- verter in continuous mode. 2.set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conversion of the selected channel. note: changing the a/d channel during conver- sion will stop the current conversion and start con- version of the newly selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? an interrupt request is generated if the ite bit is set. ? the result is in the adcdr registers and re- mains valid until the next conversion has end- ed. to read the 10 bits, perform the following steps: 1. wait for interrupt or poll the eoc bit 2. read adcdrlsb 3. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. to read only 8 bits, perform the following steps: 1. wait for interrupt 2. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. changing the conversion channel the application can change channels during con- version. in this case the current conversion is stopped and the a/d converter starts converting the newly selected channel. adccr consistency if an end of conversion event occurs after soft- ware has read the adcdrlsb but before it has read the adcdrmsb, there would be a risk that the two values read would belong to different sam- ples. to guarantee consistency: ? the adcdrmsb and the adcdrlsb are locked when the adccrlsb is read ? the adcdrmsb and the adcdrlsb are un- locked when the msb is read or when adon is reset. thus, it is mandatory to read the adcdrmsb just after reading the adcdrlsb. this is especially important in continuous mode, as the adcdr reg- ister will not be updated until the adcdrmsb is read. 10.7.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 10.7.5 interrupts note : the eoc interrupt event is connected to an interrupt vector (see interrupts chapter). it generates an interrupt if the ite bit is set in the adccsr register and the in terrupt mask in the cc register is reset (rim instruction). mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilisation time t stab (see electrical characteristics) before accurate conversions can be performed. interrupt event event flag enable control bit exit from wait exit from halt end of conversion eoc ite yes no
94/139 10-bit a/d converter (adc) (cont?d) 10.7.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrmsb register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /2 1: f adc = f cpu /4 bit 5 = adon a/d converter on this bit is set and cleared by software or by hard- ware after the end of a one shot conversion. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = ite interrupt enable this bit is set and cleared by software. 0: eoc interrupt disabled 1: eoc interrupt enabled bit 3 = oneshot one shot conversion selection this bit is set and cleared by software. 0: continuous conversion mode 1: one shot conversion mode bit 2:0 = cs[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register (adcdrmsb) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of analog converted value this register contains the msb of the converted analog value. data register (adcdrlsb) read only reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of analog converted value this register contains the lsb of the converted an- alog value. note: please refer to section 15 important notes 70 eoc speed adon ite one shot cs2 cs1 cs0 channel* cs2 cs1 cs0 0000 1001 2010 3011 4100 5101 6110 7111 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000000d1d0
95/139 11 instruction set 11.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 24. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([ $10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],# 7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3
96/139 instruction set overview (cont?d) 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 11.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
97/139 instruction set overview (cont?d) 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 25. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative
98/139 instruction set overview (cont?d) 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
99/139 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
100/139 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z
101/139 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v. they are given only as de- sign guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 53 . figure 53. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 54 . figure 54. pin input voltage c l st7 pin v in st7 pin
102/139 12.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics 12.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for exampl e, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in 103/139 12.2.3 thermal characteristics 12.3 operating conditions 12.3.1 general operating conditions (sta ndard voltage rom and flash devices) . figure 55. f cpu versus v dd for standard voltage devices 12.3.2 operating condi tions with low voltage detector (lvd) subject to general operating conditions for v dd , f cpu , and t a . refer to figure 15 on page 21 . notes: 1. not tested, guaranteed by design. 2. not tested in production, guaranteed by characterization. 3. the v dd rise time rate condition is needed to insure a correc t device power-on and lvd rese t. not tested in production. symbol ratings value unit t stg storage temperature range -65 to +150 c t j maximum junction temperature 175 c symbol parameter conditions min typ max unit v dd operating supply voltage f cpu = 8 mhz 455.5 v dda analog reference voltage v dd v dd v ssa analog reference voltage v ss v ss f cpu operating frequency f osc = 12mhz 8 mhz f osc = 6mhz 4 t a ambient temperature range 070c symbol parameter conditions min typ 1) max unit v it+ low voltage reset threshold (v dd rising) v dd max. variation 50v/ms 3.6 3.8 3.95 v v it- low voltage reset threshold (v dd falling) v dd max. variation 50v/ms 3.45 3.65 3.8 v v hyst hysteresis (v it+ - v it- ) 120 2) 150 2) 180 2) mv vt por v dd rise time rate 3) 0.5 50 v/ms f cpu [mhz] supply voltage [v] 8 4 2 0 2.5 3.0 3.5 4 4.5 5 5.5 functionality not guaranteed in this area functionality guaranteed in this area (unless otherwise specified in the tables of parametric data)
104/139 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). note 1: typical data are based on t a =25c and not tested in production note 2: data based on design simulati on, not tested in production. note 3: usb transceiver and adc are powered down. note 4: low voltage reset function enabled. cpu in halt mode. current consumption of exter nal pull-up (1.5kohms to usbvcc) and pull-down (15kohms to v ssa ) not included. figure 56. typ. i dd in run at 4 and 8 mhz f cpu figure 57. typ. i dd in wait at 4 and 8 mhz f cpu symbol parameter conditions typ 1) max unit ? i dd( ? ta) supply current variation vs . temperature constant v dd and f cpu 10 % i dd cpu run mode i/os in input mode. usb transceiver and lvd disabled f cpu = 4 mhz 6 8 ma f cpu = 8 mhz 8 14 lvd enabled. usb in transmission 2) f cpu = 4 mhz 13 18 ma f cpu = 8 mhz 15 24 ma cpu wait mode 2) i/os in input mode. usb transceiver and lvd disabled f cpu = 8 mhz 7 12 ma lvd enabled. usb in transmission f cpu = 8 mhz 14 22 ma cpu halt mode 3) with lvd 130 200 a without lvd 30 50 usb suspend mode 4) 130 200 a i dd(adc) adc supply current when converting f adc =4mhz 1000 2) a 0 2 4 6 8 10 12 3 3.5 4 4.5 5 5.5 6 vdd (v) idd (ma) idd run at fcpu=4 mhz idd run at fcpu=8 mhz 0 1 2 3 4 5 6 7 8 9 10 1234567 vdd (v) idd (ma) idd wfi at fcpu=4 mhz idd wfi at fcpu=8 mhz
105/139 12.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 12.5.1 general timings 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instru ction execution. 12.5.2 control timing characteristics note 1: the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. note 2: not tested in production, guaranteed by design. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time f cpu =8mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = ? t c(inst) + 10 t cpu f cpu =8mhz 10 22 t cpu 1.25 2.75 s control timings symbol parameter conditions value unit min 2) typ. 2) max 2) f osc oscillator frequency 12 mhz f cpu operating frequency 8 mhz t rl external reset input pulse width 1.5 t cpu t porl internal power reset duration 514 t cpu t rstl reset pin output pulse width 10 s t wdg watchdog time-out f cpu = 8mhz 65536 8.192 4194304 524.288 t cpu ms t oxov crystal oscillator start-up time 20 30 40 ms t ddr power up rise time from v dd = 0 to 4v 100 ms
106/139 clock and timing characteristics (cont?d) 12.5.3 external clock source note: 1. refer to figure 58 for more information. figure 58. typical application with an external clock source 12.5.4 crystal oscillator output drive level figure 59. typical application with a crystal resonator symbol parameter conditions min typ max unit v oscinh oscin input pin high level voltage see figure 58 0.7xv dd v dd v v oscinl oscin input pin low level voltage v ss 0.3xv dd t w(oscinh) t w(oscinl) oscin high or low time 1) 15 ns t r(oscin) t f(oscin) oscin rise or fall time 1) 15 i l oscx input leakage current v ss v in v dd 1 a oscin oscout f osc external st72xxx clock source not connected internally v oscinl v oscinh t r(oscin) t f(oscin) t w(oscinh) t w(oscinl) i l 90% 10% symbol parameter conditions typ unit p oscout oscillator oscout pin drive level at 5v / 25c 1 mw oscout oscin f osc c l1 c l2 i 2 r f st72xxx resonator 200 ? 107/139 12.6 memory characteristics subject to general operating conditions for f cpu , and t a unless otherwise specified. 12.6.1 ram and hardware registers note 1: guaranteed by design. not tested in production. 12.6.2 flash memory operating conditions: f cpu = 8 mhz. note: 1. refer to the flash programming reference manual for the typical hdflash programming and erase tim- ing values. figure 60. two typical applications with v pp pin 1) note 1: when the icp mode is not requi red by the application, v pp pin must be tied to v ss . symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 2.0 v dual voltage flash memory 1) symbol parameter conditions min typ max unit f cpu operating frequency read mode 8 mhz write / erase mode, t a =25c 8 v pp programming voltage 4.0v <= v dd <= 5.5v 11.4 12.6 v i pp v pp current write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a 55c 40 years n rw write erase cycles t a =25c 100 cycles v pp st72xxx 10k ? programming tool v pp st72xxx
108/139 12.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 12.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 12.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). 12.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, pdip42, f cpu = 8mhz conforms to iec 1000-4-2 2b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v ss pins to induce a func- tional disturbance v dd = 5v, t a = +25c, pdip42, f cpu = 8mhz conforms to iec 1000-4-4 2b symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 6/4mhz 12/8mhz s emi peak level v dd = 5v, t a = +25c, pdip42 package, conforming to sae j 1752/3 0.1mhz to 30mhz 35 38 db v 30mhz to 130mhz 42 45 130mhz to 1ghz 28 32 sae emi level 4 4.5 -
109/139 emc characteristics (cont?d) 12.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 12.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22- a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 12.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a
110/139 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 61. two typical applications with unused i/o pin figure 62. typical i pu vs. v dd with v in =v ss figure 63. typical r pu vs. v dd with v in =v ss notes: 1. configuration not recommended, all unused pins must be kept at a fixed voltage: using t he output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 61 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristic s, not tested in production. this value depends on v dd and tem- perature values. 2. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 62 ). this data is based on characterization results. 3. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. symbol parameter conditions min typ max unit v il input low level voltage 0.3xv dd v v ih input high level voltage 0.7xv dd v in input voltage true open drain i/o pins v ss 6.0 v other i/o pins v dd v hys schmitt trigger voltage hysteresis 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption 1) floating input mode 400 r pu weak pull-up equivalent resistor 2) v in = v ss v dd =5v 50 80 150 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 25 t w(it)in external interrupt pulse time 3) 1t cpu 10k ? unused i/o port st72xxx 10k ? unused i/o port st72xxx v dd -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) ipu (a) 0 20 40 60 80 100 120 140 160 180 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) rpu (k )
111/139 i/o port pin characteristics (cont?d) 12.8.2 output driving current subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. figure 64. typ. v ol at v dd =5v (std. port) figure 65. typ. v ol at v dd =5v (high-sink) figure 66. typ. v dd -v oh at v dd =5v (std. port) figure 67. typ. v dd -v oh at v dd =5v (high-sink) notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 12.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 12.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when up to 8 pins are sunk at same time (see figure 64 ) v dd =5v i io =+5ma 1.3 v i io =+2ma 0.4 output low level voltage for a high sink i/o pin when up to4 pins are sunk at same time (see figure 65 ) i io =+20ma 1.3 i io =+8ma 0.4 v oh 2) output high level voltage for an i/o pin when up to 8 pins are sourced at same time (see figure 66 ) i io =-5ma v dd -2.0 i io =-2ma v dd -0.8 0 0.2 0.4 0.6 0.8 1 1.2 0123456789 i io (ma) v ol (v) at t a 25c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 i io (ma) v ol (v) at t a =25c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 i io (ma) v dd -v oh (v) at t a =25c 0 0.05 0.1 0.15 0.2 0.25 0.3 -8 -7 -6 -5 -4 -3 -2 -1 0 i io (ma) v dd -v oh (v) t=25c
112/139 i/o port pin characteristics (cont?d) figure 68. typical v ol vs. v dd (standard port) figure 69. typical v ol vs. v dd (high-sink port) figure 70. typical v dd -v oh vs. v dd (standard port) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 3.5 4 4.5 5 5.5 6 v dd (v) v ol (v) at i io =5ma 0 0.05 0.1 0.15 0.2 0.25 3.5 4 4.5 5 5.5 6 v dd (v) v ol (v) at i io =2ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 3.5 4 4.5 5 5.5 6 v dd (v) v ol (v) at i io =20ma 0 0.05 0.1 0.15 0.2 0.25 0.3 3.5 4 4.5 5 5.5 6 v dd (v) v ol high sink port (v) at i io =8ma 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 3.5 4 4.5 5 5.5 6 v dd (v) v dd -v oh (v) at i io =-2ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 3.544.555.56 v dd (v) v dd -v oh (v) at i io =-5ma
113/139 i/o port pin characteristics (cont?d) figure 71. typical v dd -v oh vs. v dd (high sink port) 12.9 control pin characteristics 12.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v, not tested in production. 2. data guaranteed by design. 3. hysteresis voltage between schmitt tr igger switching levels. based on c haracterization results, not tested. 4. the i io current sunk must always respect t he absolute maximum rating specified in section 12.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 72 ). this data is based on characteriza tion results, not tested in production. 6. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 3.5 4 4.5 5 5.5 6 vdd (v) v dd -v od (v) at i io =-2ma 0 0.05 0.1 0.15 0.2 0.25 3.5 4 4.5 5 5.5 6 vdd (v) v dd -v od (v) at i io =-5ma symbol parameter conditions min typ 1) max unit v ih input high level voltage 0.7xv dd v dd v v il input low voltage v ss 0.3xv dd v v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) (see figure 73 , figure 74 ) v dd =5v i io =5ma 1 2) v i io =2ma 0.4 2) r on weak pull-up equivalent resistor 5) v in = v ss 60 k ? t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc s t h(rstl)in external reset pulse hold time 6) 10 s
114/139 control pin characteristics (cont?d) figure 72. typical i on vs. v dd with v in =v ss figure 73. typical v ol at v dd =5v (reset ) figure 74. typical v ol vs. v dd (reset ) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) ipu (a) 25c 0.0 0.2 0.4 0.6 0.8 1.0 0123456789 i io (ma) v ol (v) 0 0.05 0.1 0.15 0.2 0.25 0.3 3 3.5 4 4.5 5 5.5 6 6.5 v dd (v) v ol (v) at i io =2ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 33.544.555.566.5 v dd (v) v ol (v) at i io =5ma
115/139 control pin characteristics (cont?d) figure 75. reset pin protection when lvd is enabled. 1)2)3)4) figure 76. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.9.1 on page 113 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 102 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to the reset circuit have been applied (see notes above). ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? 0.01 f st72xxx pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode 5) 0.01 f external reset circuit user st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode 5) required
116/139 12.10 timer peripheral characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 12.10.1 8-bit pwm-art auto-reload timer symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 res pwm pwm resolution 8bit v os pwm/dac output step voltage v dd =5v, res=8 bits 20 mv
117/139 12.11 communication interface characteristics 12.11.1 usb - universal bus interface (operating conditions t a = 0 to +70c, v dd = 4.0 to 5.25v unless otherwise specified) notes 1. rl is the load connected on the usb drivers. 2. all the voltages are measured from the local ground potential. 3. not tested in production, guaranteed by design. 4. to improve emc performance (noise immunity), it is recommended to connect a 100nf capacitor to the usbvcc pin. figure 77. usb: data signal rise and fall time table 26. usb: low-speed electrical characteristics note 1: measured from 10% to 90% of the data signal. for more detailed informati ons, please refer to chapter 7 (elec- trical) of the usb spec ification (version 1.1). usb dc electrical characteristics parameter symbol conditions 2) min. max. unit differential input sensit ivity vdi i(d+, d-) 0.2 3) v differential common mode range vcm includes vdi range 0.8 3) 2.5 3) v single ended receiver threshold vse 0.8 3) 2.0 3) v static output low vol rl of 1.5k ohms to 3.6v 1) 0.3 v static output high voh rl of 15k ohms to v ss 1) 2.8 3.6 v usbvcc: voltage level 4) usbv v dd =5v 3.00 3.60 v differential data lines v ss tf tr crossover points vcrs parameter symbol conditions min max unit driver characteristics: rise time tr cl=50 pf 1) 75 ns cl=600 pf 1) 300 ns fall time tf cl=50 pf 1) 75 ns cl=600 pf 1) 300 ns rise/ fall time matching trfm tr/tf 80 120 % output signal crossover voltage vcrs 1.3 2.0 v
118/139 communication interface characteristics (cont?d) 12.11.2 spi - serial peripheral interface subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 78. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or charac terization results, not tested in production. 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min 1) max 1) unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in
119/139 communication interface characteristics (cont?d) figure 79. spi slave timing diagram with cpha=1 1) figure 80. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck)
120/139 12.12 10-bit adc characteristics subject to general operating conditions for v dd, f cpu , and t a unless otherwise specified figure 81. r ain max. vs f adc with c ain =0pf 4) figure 82. recommended c ain /r ain values 5) figure 83. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resist or will downgrade the adc accuracy (es pecially for resistance greater than 10k ? ). data based on characterization resu lts, not tested in production. 4. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad ca- pacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 5. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization and to allow the use of a larger serial resistor (r ain) . it is valid for all f adc frequencies 4mhz. 6. please refer to important notes on conversion speed, section 15.2 and also to figure 92. on page 137 for details on silicon revision identification. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 0.4 4 mhz v ain conversion voltage range 2) v ssa v dda v r ain external input impedance see figure 81 and figure 82 3)4)5) k ? c ain external capacitor on analog input pf f ain variation frequency of analog input signal hz c adc internal sample and hold capacitor 6 pf t conv 6) conversion time flash silicon rev. g devices f adc =4mhz 4 s 16 1/f adc conversion time flash silicon rev. x and rom rev. z devices 28 s 112 1/f adc 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 4 mhz 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion 2k ?( max ) c ain
121/139 adc characteristics (cont?d) 12.12.0.1 analog power supply and reference pins depending on the mcu pin count, the package may feature separate v dda and v ssa analog pow- er supply pins. these pins supply power to the a/d converter cell and function as the high and low ref- erence voltages for the conversion. in some pack- ages v dda and v ssa pins are not available (refer to table 1, ?device pin description,? on page 8 ). in this case the analog supply and reference pads are internally bonded to the v dd and v ss pins. separation of the digital and analog power pins al- low board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 10.7.3.2 pcb design guidelines ). 12.12.0.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to sh ield the the noise-sensi- tive, analog physical interface from noise-generat- ing cmos logic signals. ? use separate digital and analog planes. the an- alog ground plane should be connected to the digital ground plane via a single point on the pcb. ? filter power to the analog power planes. the best solution is to conn ect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and 10pf capacitors as close as possible to the st7 power supply pins and a 10f capacitor close to the power source (see figure 84 ). ? the analog and digital power supplies should be connected in a star nework. do not use a resis- tor, as v dda is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. ? properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. 12.12.0.3 specific application design guidelines ? when a usb transmission is taking place during a/d conversion, the noise caused on the analog power supply by the usb transmission may re- sult in a loss of adc accuracy. ? if the usb is used to supply power to the appli- cation, this causes noise which may result in a loss of adc accuracy. figure 84. power supply filtering v ss v dd 0.1 f 10pf v dd st72xxx v dda v ssa power supply source st7 digital noise filtering external noise filtering 10 f 0.1 f 10pf
122/139 adc characteristics (cont?d) 12.12.1 adc accuracy table 27. f cpu =8 mhz, f adc =4 mhz r ain < 10 k ? 2) notes: 1. not tested in production, guar anteed by characterization. all accuracy measurements are taken with the mcu in wait mode (no i/o switching) and when adequat e low-pass filtering is present (0.1 f capacitor between v dd /v dda and v ss / v ssa ). outside these conditions, a degree of mi crocontroller noise may result, causi ng accuracy errors which will vary based on board layout and t he type of cpu activity. 2. adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins significantly reduces the accu racy of the conversion being per- formed on another analog input. for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 4 lsb for each 10k ? increase of the external analog source impedance. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive inject ion current within the limits spec- ified for i inj(pin) and i inj(pin) in section 12.8 does not affect the adc accuracy. symbol parameter conditions typ max 1) unit |e t | total unadjusted error v dd = 4v-5.5v 3 lsb |e o | offset error 12 |e g | gain error 0.7 2 |e d | differential linearity error 1.3 2 |e l | integral linearity error 2.9 5
123/139 figure 85. adc accuracy characteristics e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dda v ssa
124/139 13 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level in- terconnect. the category of second level inter- connect is marked on the package and on the in- ner box label, in comp liance with jedec standard jesd97. the maximum rati ngs related to solder- ing conditions are also marked on the inner box la- bel. ecopack is an st tra demark. ecopack speci- fications are available at: www.st.com 13.1 package mechanical data figure 86. 44-pin low profile quad flat package dim. mm inches 1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.000 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.80 0.031 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 note 1. values in inches are converted from mm and rounded to 3 decimal digits. a a2 a1 b e l1 l h c e e1 d d1
125/139 figure 87. 42-pin plastic dual in-line package, shrink 600-mil width figure 88. 34-pin plastic small outline package, shrink 300-mil width dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.015 0.018 0.022 b2 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n 42 e e1 ea eb e 0.015 gage plane ec eb d e b b2 a2 a1 c l a dim. mm inches min typ max min typ max a 2.464 2.642 0.097 0.104 a1 0.127 0.292 0.005 0.012 b 0.356 0.483 0.014 0.019 c 0.231 0.318 0.009 0.013 d 17.72 9 18.05 9 0.698 0.711 e 7.417 7.595 0.292 0.299 e 1.016 0.040 h 10.16 0 10.41 4 0.400 0.410 h 0.635 0.737 0.025 0.029 0 8 0 8 l 0.610 1.016 0.024 0.040 number of pins n 34 h x 45 c l a a a1 e b d h e
126/139 figure 89. 32-pin plastic dual in-line package, shrink 400-mil width figure 90. 20-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 20 eh a a1 b e d c h x 45 l a
127/139 figure 91. 20-pin plastic dual in-line package, 300-mil width dim. mm inches min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.16 26.92 0.980 1.030 1.060 d1 0.13 0.005 e 2.54 0.100 eb 10.92 0.430 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 20 e1 d d1 b e a a1 l a2 c eb 11 10 1 20 b2
128/139 14 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). st7262 devices are rom versions. st72f62 flash devices ar e shipped to custom- ers with a default content (ffh). this implies that flash devices have to be configured by the cus- tomer using the option byte while the rom devic- es are factory-configured. 14.1 option byte the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode using a standard st7 programming tool. the default content of the flash is fixed to ffh. this means that all the options have ?1? as their default value. bits 7:6 = reserved. bit 5 = wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware enabled 1: software enabled bit 4 = nest this option bit selects the nested interrupts fea- ture. 0: nested interrupt feature disabled 1: nested interrupt feature enabled bit 3 = lvd low voltage detector selection this option bit selects the lvd. 0: lvd enabled 1: lvd disabled bit 2= reserved. bit 1 = osc12/6 oscillator selection this option bit selects the clock divider used to drive the usb interface at 6mhz. 0: 6 mhz oscillator (no divider for usb) 1: 12 mhz oscillator (2 divider for usb) bit 0 = fmp_r memory readout protection readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.3.1 on page 14 for more de- tails. 0: read-out protection enabled 1: read-out protection disabled 14.2 device ordering informat ion and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all un- used bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. 70 -- wdg sw nest lvd - osc 12/6 fmp_ r
129/139 device configuration an d ordering information (cont?d) table 28. supported part numbers part number program memory (bytes) ram (bytes) package st72f623f2b1 8k flash 384 pdip20 st72f623f2m1 so20 st72f622l2m1 so34 ST72F621K4B1 16k flash 768 pdip32 st72f621l4m1 so34 st72f621j4b1 16k flash 768 pdip42 st72f621j4t1 lqfp44 st72623f2b1 8k rom 384 pdip20 st72623f2m1 so20 st72622l2m1 so34 st72621k4b1 16k rom 768 pdip32 st72621l4m1 so34 st72621j4b1 16k rom 768 pdip42 st72621j4t1 lqfp44
130/139 14.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st see table 29 and table 30 for more details. table 29. stmicroelectronics tools features note : 1. in-circuit programming (icp) interface for flash devices. table 30. dedicated stmicroe lectronics development tools note : 1. add suffix /eu or /us for the power supply for your region. in-circuit emulation p rogramming capability 1) software included st7 emulator yes, powerful emulation features including trace/ logic analyzer no st7 cd rom with: ? st7 assembly toolchain ? stvd7 powerful source level debugger for win 3.1, win 9x and nt ? c compiler demo versions ? windows programming tools for win 3.1, win 9x and nt st7 programming board no yes (all packages) supported products evaluation board st7 emulator st7 programming board active probe & target emulation board st7262 st7mdtuls-eval st7mdtu2-emu2b st7mdtu2-epb 1) st7mdtu2-dbe2b
131/139 st7262 microcontroller option list (last update: march 2006) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/p ackage (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " authorized characters are letters, di gits, '.', '-', '/' and spaces only. max character count: s020 (8 char. max) : _ _ _ _ _ _ _ _ s034 (13 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ dip20/dip32/lqfp44 (10 char. max) : _ _ _ _ _ _ _ _ _ _ dip42 (16 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ watchdog selection: [ ] software activation [ ] hardware activation nested interrupt: [ ] enabled [ ] disabled lvd reset : [ ] disabled [ ] enabled oscillator selection : [ ] 6 mhz. [ ] 12 mhz. readout protection: [ ] enabled [ ] disabled date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . please download the latest versio n of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list --------------------------------- rom device: --------------------------------- | | ----------------------------------------- 8k ----------------------------------------- | | ----------------------------------------- 16k ----------------------------------------- sdip20: | [ ] st72623f2b1 | so20: | [ ] st72623f2m1 | sdip32: | | [ ] st72621k4b1 so34: | [ ] st72622l2m1 | [ ] st72621l4m1 sdip42: | | [ ] st72621j4b1 lqfp44: | | [ ] st72621j4t1 --------------------------------- die form: --------------------------------- | | ------------------------------------------ 8k ------------------------------------------ | | ------------------------------------------ 16k ------------------------------------------ 20-pin: | [ ] | 32-pin: | [ ] | [ ] 34-pin: | [ ] | [ ] 42-pin: | [ ] | [ ] 44-pin: | [ ] | [ ] ------------------------------------------------------------------------ packaged product (do not specify for dip package) ------------------------------------------------------------------------ | | ----------------------------------------------------- die product (dice tested at 25c only) ----------------------------------------------------- [ ] tape & reel [ ] tray (lqfp package only) | [ ] tape & reel [ ] tube (so package only) | [ ] inked wafer | [ ] sawn wafer on sticky foil
132/139 14.4 st7 application notes table 31. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative in- put voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16 bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art
133/139 an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain table 31. st7 application notes identification description
134/139 an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1477 emulated data eeprom with xflash memory an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma-delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 31. st7 application notes identification description
135/139 15 important notes refer to table 32 which provides a list of the trace codes for each of the recent silicon revisions. silicon revisions are identifiable: ? on the device package, by the last letter of the trace code marked on the device package. ? on the box, by the last 3 digits of the internal sales type printed in the box label. see also figure 92. on page 137 table 32. device identification 15.1 a/ d converter accuracy for first conversion description when the adc is enabled after being powered down (for example when waking up from halt, active-halt or setting the adon bit in the ad- ccsr register), the first conversion (8-bit or 10- bit) accuracy does not meet the accuracy specified in the datasheet. workaround in order to have the accuracy specified in the da- tasheet, the first conversion after a adc switch-on has to be ignored. note: this limitation does not a pply to flash silicon rev. g devices (see table 32 ). 15.2 a/d converter conversion speed description following a change in the fabrication location, the typical adc conversion s peed value for flash de- vices has improved from a previous value of 28s to 4s. when migrating software fr om rev x to rev g de- vices (refer to table 32 ) care should be taken when using adc interrupts. workaround firstly, on rev g devices, only the use of one- shot conversion mode is recommended in con- nection with adc interrupts. in continuous conversion mode, to avoid getting trapped in a continuous interrupt, the adc inter- rupt routine must always have sufficient time to ex- ecute completely before the next adc conversion interrupt, especially if the adc interrupt is disabled outside of this routine. with the shorter conversion speed value, the interrupt may not be serviced fast enough. for this reason, on rev g devices, the continuous conversion mode is not recommend- ed in connection with adc interrupts. secondly, in the interests of keeping code portable between all flash/rom versions, using the adc as a source of a delayed trigger event is not ad- vised. however, in such a scenario, a delay loop should be inserted for rev g flash devices to en- sure that the timing remains the same for any such adc delayed trigger events. device type (silicon rev.) trace code marked on device/ internal sales type on box label flash devices (rev g) (latest flash silicon) ?xxxxxxxxxg? / 72f62xxxxx$x4 flash devices (rev x) (previous flash silicon) ?xxxxxxxxxx? / 72f62xxxxx$x8 ?xxxxxxxxxx? / 72f62xxxxx$x9 rom devices (rev z) ?xxxxxxxxxz? / 7262xxxxx$x2 ?xxxxxxxxxz? / 7262xxxxx$x3
136/139 15.3 sci wrong break duration description a single break character is sent by setting and re- setting the sbk bit in th e scicr2 register. in some cases, the break character may have a long- er duration than expected: ? 20 bits instead of 10 bits if m=0 ? 22 bits instead of 11 bits if m=1. in the same way, as lo ng as the sbk bit is set, break characters are sent to the tdo pin. this may lead to generate one break more than expect- ed. this affects all silicon revisions. occurrence the occurrence of the problem is random and pro- portional to the baudrate. with a transmit frequen- cy of 19200 baud (f cpu =8mhz and sci- brr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with the communication protocol in the application, soft- ware can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the applica- tion is not doing anything between the idle and the break. this can be ensured by temporarily disa- bling interrupts. the exact sequence is: ? disable interrupts ? reset and set te (idle request) ? set and reset sbk (break request) ? re-enable interrupts 15.4 unexpected reset fetch if an interrupt request occurs while a "pop cc" in- struction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. this affects all silicon revisions. workaround to solve this issue, a "pop cc" instruction must always be preceded by a "sim" instruction. 15.5 halt mode power consumption with adc on if the a/d converter is being used when halt mode is entered, the power consumption in halt mode may exceed the maximum sp ecified in the datash- eet. this affects all silicon revisions. workaround switch off the adc by software (adon=0) before executing a halt instruction.
137/139 figure 92. revision marking on box label and device marking note: refer also to table 32 on page 135 for additional revision identification notes type xxxx internalxxx$xx trace code last 2 digits after $ in internal sales type indicate silicon rev. last letter of trace code on device indicates silicon rev. on box label
138/139 16 revision history description of the changes between the current re lease of the specification and the previous one. date revision description of changes 23-sep-2005 3.0 clarification of flash read-out protection in section 4.3.1 on page 14 removed ?optional? for v dd in figure 9 on page 15 added one note in ?low voltage reset? on page 21 added caution to ?external clock and event detector mode? on page 47 changed section 10.4.3.3 on page 59 changed table 18 on page 64 changed section 10.5.4.3 on page 71 (noise error section) changed ?sci clock tolerance? on page 74 added ?noise error causes? on page 75 added one row for injected current on pa0 to pa7 pins in section 12.2.2 on page 102 changed ?emc characteristics? on page 108 changed figures and tables in ?package mechanical data? on page 124 changed description of fmp_r bit in section 14.1 on page 128 added section 15.1 on page 135 added section 15.3 on page 136 added note in section 10.4.2 on page 56 changed description of tc bit in section 10.5.7 on page 77 modified maximum injected current values for pa0-pa6, pa7, section 12.2.2 on page 102 reference made to the flash programming reference manual for flash timing values sec- tion 12.6.2 on page 107 updated option list added figures and notes for reset pin protection when lvd is enabled/disabled page 115 added ecopack information in section 13 on page 124 modified i s value and corresponding note in section 12.8.1 on page 110 20-mar-2006 4.0 all low voltage devices and characteristics removed addition of rs resistor in figure 59. on page 106 additional note added below table 4 on page 20 note added at end of section 10.7.6 on page 94 referring to important notes section 12.5.4 crystal oscillator output drive level modified t conv values modifed in section 12.12 on page 120 according to flash/rom silicon revison important notes modified s howing device identification important note related to a/d converter conversion speed added, section 15.2 on page 135 weak pull-up equivalent resi stor values modified, section 12.9.1 on page 113 graph in figure 72 on page 114 updated updated option list notes updated for section 12.9.1 , section 12.11.1 , section 12.11.2 , section 12.12.1 figures modified for reset pin prot ection when lvd is enabled/disabled page 115 all fastrom options removed
139/139 notes: please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or li fe sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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